1. Field of the Invention
This invention relates to improvements in methods for providing a smooth transition from open-loop step-up of a system frequency to closed-loop phase-locked loop (PLL) control by synchronization of the voltage-controlled oscillator (VCO) when the open-loop frequency is within pull-in range, and to circuits for accomplishing the same.
2. Description of the Prior Art
Although the present invention pertains to voltage controlled oscillator (VCO) synchronization of phase-locked loop (PLL) systems in general, it finds particular application in conjunction with polyphase DC motors, particularly of the brushless, sensorless, three-phase type used for rotating data media, such as are found in computer-related applications, such as hard disc drives, CD ROM drives, floppy disc drives, and the like. In such computer applications, three-phase, brushless, sensorless DC motors are becoming more popular, due to their reliability, low weight, and accuracy.
Brushless DC motors are commonly driven by a speed-controller that utilizes two functional loops: an overall speed-control loop, typically a PLL circuit, and a phase switching loop. A typical prior art motor speed-controller 10 is shown in FIG. 1. The outer speed control loop 13 has a phase comparator 11 that compares a reference frequency, F.sub.REF, applied to an input line 14 with a signal developed by a signal processor 20 from the stator windings of a motor 19. The phase difference signal developed by the phase comparator 11 is filtered by a filter 12 to drive switch logic circuitry 15, which in turn drives the motor 19 via appropriate drive circuitry 16. The outer speed control loop 13 ensures that the desired motor speed, set by the reference frequency, F.sub.REF, on a line 14, is maintained. The phase switching inner loop 17 generates a timing signal that is sent to the switch logic circuit 15 to time the commutations in the stator coils 21 that drive the motor 19. In order to properly time the commutations in the circuit 19, however, the exact position of the rotor 18 must be determined. In the past, sensors, such as Hall or optical sensors, have been used to determine the position of the rotor. A more recent approach uses back emf information derived from selected ones of the stator coils 21 of the motor 19 to determine the location of the rotor 18. In such approach, as the magnetic rotor 18 passes a "floating" stator coil, it acts as a generator in regard to the coil and impresses an electromotive force or "back emf" on the coil. The back emf signal is processed and routed to the switching logic system to obtain the correct phase-switching. The back emf detection information not only enables the position of the rotor 18 to be determined, but the speed of the motor 21, as well. This motor speed information is fed back to the phase-comparator 11 of the outer speed-control loop 13 to maintain the desired motor operating speed.
The inner phase-switching loop 17 can be implemented in several ways. As mentioned, the clock signal for phase-switching in the inner loop may be provided by filtering the back emf of the motor 19 and extracting timing information with a signal processor 20. This involves determining the "zero-crossing" of the back emf, and using delays to control the timing of the switching.
A more sophisticated approach shown in FIG. 2 is similar to that of U.S. Pat. No. 4,928,043, and uses a phase-locked loop (PLL) 35 to phase-track the back emf, in place of the signal processor 20. The phase-locked loop 35 includes a filter 32 connected to receive a signal derived from the back emf generated by the rotor 18 of the motor 19, to produce an output to a phase comparator 34. The phase comparator 34 compares the back emf signal with a desired phase signal (not shown) and produces an output to a second filter 36 to provide an error voltage to a voltage controlled oscillator (VCO) 38. In this approach, the back emf is used as an input to the PLL 35, and the output of the PLL 35 is fed to the phase-switching logic circuitry 15. In this way, the phase-switching logic circuitry 15 is synchronized to the back emf. This configuration offers better performance, since it reduces "phase-jitter", rapid, uncontrolled rotor movements due to imprecisely-timed phase-switching. The drawback of this approach is that at low motor speeds that occur when the motor 19 is first starting, the back emf signal is not of sufficient magnitude to drive the loop. In addition, as with any PLL loop, "lock" can be established in only a limited range of frequencies, and therefore during most of the start-up phase, the switching frequency is outside (lower than) the "lock"range. Thus, the motor 19 is generally ramped-up to speed open-loop, with the timing signal to the switching logic being provided by an external clock. The desired final operating state is a closed-loop mode in which the clock to the phase-switching is provided by a voltage-controlled oscillator (VCO) 38. What is needed is a way to produce a transition from open-loop operation to closed-loop operation without significant error in the switching timing that makes the loop incapable of locking and which may consequently stall the motor.